1. Field of the Invention
This present invention relates generally to metal insulator semiconductor (MIS) devices. More particularly, the present invention relates to systems and methods for determining the capacitance versus voltage of dielectric materials forming the gate insulation structure of the MIS devices. Even more particularly, the present invention relates to circuits and systems for determining from the capacitance versus voltage the thickness of ultra-thin gate oxides of a metal oxide semiconductor (MOS) transistor.
2. Description of Related Art
Characterization of MOS transistors is critical to the verification of the manufacturing process design to the resulting integrated circuits. Capacitance-voltage measurement is fundamental to determining the device characteristics of the MOS transistors.
As the manufacturing processes are improved, the device sizes of the MOS transistors are decreasing and the gate insulation or gate oxide is becoming thinner. The gate capacitance thus is becoming more difficult to determine. The thinner insulator of the MOS device results in the direct tunneling leakage current increasing exponentially and the parasitic capacitances of the MOS device no longer being able to be ignored.
Refer now to FIG. 1 for a review of the test structure of the prior art for determining the capacitance of the insulating structure of a MOS device versus an applied voltage. The test structure in this case is essentially a MOS capacitor formed of a MOS transistor having the gate as the one plate of the capacitor, the gate oxide as the insulator, and the source, drain, and the intervening channel as the second plate. A substrate 3, generally a lightly doped semiconductor crystalline wafer, has a well 5 formed with lightly doped impurities to act as a bulk semiconductor the for the test structure. Shallow trench isolation regions 15 are formed in the surface of the substrate 3 within the well area 5 to demarcate the test structure. A well pick-up contact 20 is formed in the well area 5 by diffusion of heavily doped impurities of the same polarity as the well area 5 to provide a low resistivity path for connection to the well area 5. A source/drain region 10 are formed by a diffusion of a heavily doped impurity of a polarity opposite that of the well are 5 adjacent to the shallow trench isolation regions 15.
A gate oxide 25 is constructed at the surface of the substrate in the area above the well 5 and between and overlapping the source/drain region 10. A conductive gate 30 is formed of highly doped polycrystalline silicon on the surface of the gate oxide 25 above the well 5 and between and overlapping the source/drain region 10.
The Agilent Technologies Impedance Measurement Handbook, Application Note 5950, staff, Agilent Technologies Co. Ltd., Palo Alto, Ac 943303, copyright 2000, pp. 5-12-5-14, illustrates a capacitance-voltage test system 35. The capacitance voltage system 35 has an AC voltage source 40 and a DC biasing voltage source 45 that are added to form the stimulus that is applied through the stimulus terminals 50 and 55 to the source/drain region 10 and the well pick-up 20. The sense terminal 60 is connected to the gate 30 to provide a return path for the currents of generated by the stimulus voltages. The voltage meter 65 is connected between the stimulus terminal 55 and the sense terminal 60 to measure the voltage developed across the test structure. The current meter 70 is connected to terminal 60 and the ground reference terminal to sense the current flowing through the test structure. The voltage meter 65 and the current meter 70 are capable of measuring the AC amplitude and phase to determine the capacitance of the test structure. The DC biasing voltage source 45 is swept to force the channel area 22 beneath the gate oxide 25 to be forced from the accumulation of the majority carriers in the channel area 22, to a depletion of the majority carriers in the channel area 22, to an inversion to accumulate the minority carriers of the channel area 22. The voltmeter 65 and the current meter 70 readings are logged for each voltage of the biasing voltage source 45 based on the frequency of the AC voltage source 40. The capacitance is determined for each biasing level.
Referring to FIG. 6a for an illustration of the equivalent circuit for the structure of the prior art. The MOS capacitor formed of the MOS transistor is represented as the capacitor Cg 300 and the parasitic capacitance is represented by the capacitor Cp 305. The AC voltage source 40 and the DC biasing voltage source 45 are added and applied to the terminal 55. In the structure of the prior art as shown the parasitic capacitor Cp 305 can not be easily eliminated in the determination of the MOS capacitance Cg 300 formed of the MOS transistor. The MOS capacitor Cg 300 and the parasitic capacitance Cp 305 are connected to the sense terminal 60 to receive the current generated by the voltages of the AC voltage source 40 and the DC biasing voltage source 45 applied to the terminal 55. As shown, the measured capacitance is the sum of the capacitances of the MOS capacitor Cg 300 and the parasitic capacitor Cp 305.
Refer now to FIGS. 2a and 2b for a discussion of the effects of the thickness of the gate oxide 25 of FIG. 1. FIG. 2a illustrates the gate capacitance of the test structure, where the test structure represents an NMOS transistor having a p-type well 5. FIG. 2b illustrates a gate capacitance of the test structure, where the test structure represents a PMOS transistor having an n-type well 5. The area of the test structure of FIGS. 2a and 2b used to determine the gate capacitance is approximately 400 μm2. For test structures having gate oxide 25 of approximately 20 Å, the capacitance 75 of the NMOS device of FIG. 2a remains consistent across the range of DC biasing voltage applied to the source/drain region 10 and the well pickup 20. However, for a gate oxide 25 of 17 Å, the capacitance 80 shows a distortion 82 resulting from the dominance of the large gate leakage current.
Similarly, for the PMOS device of FIG. 2b, where the test structures have a gate oxide 25 of approximately 20 Å, the capacitance 85 of the remains consistent across the range of DC biasing voltage applied to the source/drain region 10 and the well pick-up 20. However, for a gate oxide 25 of 17 Å, the capacitance 90 shows a distortion 92 resulting from the large gate leakage current.
To minimize the effects of the larger leakage current because of the thinner oxide, the test structure is made smaller (<100 μm2). This causes a further inaccuracy in the measurement of the gate capacitance since the parasitic capacitances now begin to dominate.
U.S. Pat. No. 6,472,236 (Wang, et al.) describes a system and method for determining an effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. Test MOS stacks are formed with each MOS stack having a dielectric structure comprised of a stack of two dielectric materials. The time for deposition of the first dielectric material is varied in the formation of the MOS stacks while the second dielectric material is maintained to be substantially constant for the test MOS stacks. A total effective oxide thickness is measured for each of the MOS stacks. A first graph having total effective oxide thickness as a first axis and having deposition time for forming the first dielectric structure as a second axis is generated by plotting the respective total effective oxide thickness versus the respective deposition time for forming the first dielectric material for each of the test MOS stacks. The respective second effective oxide thickness of the respective second dielectric structure that is substantially same for each of test MOS stacks is determined from an intercept of the first axis of total effective oxide thickness when deposition time for forming the first dielectric material of the second axis is substantially zero in the first graph.
U.S. Pat. No. 6,456,105 (Tao) describes a method for determining the electrical thickness of a very thin gate oxide layer of a MOS transistor that is subject to relatively high leakage current owing to its thinness includes measuring first and second frequency-dependent capacitances C1, C2 and then using the capacitances to render a corrected capacitance. The electrical thickness is then determined the corrected capacitance, to render a comparatively more accurate value of gate oxide electrical thickness Tox.
U.S. Pat. No. 5,485,097 (Wang) illustrates a method of electrically measuring a thin oxide thickness by tunnel voltage. A predetermined value of current density is applied through the device under test. The voltage developed across the device under test is measured and the oxide electrical thickness is calculated through a predetermined calibration curve.
“MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” Yang et al., IEEE Transactions On Electron Devices, VOL. 46, NO. 7, July 1999, pp. 1500-1501, presents a technique, which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies.
“MOS C-V Characterization of Ultra-thin Gate Oxide Thickness (1.3-1.8 nm),” Choi et al., IEEE Electron Device Letters, VOL. 20, NO. 6, JUNE 1999, pp. 292-294, describes an equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultra-thin gate oxides (1.3-1.8 nm). Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator, tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.
U.S. Pat. No. 5,793,675 (Cappelletti, et al.) describes a method for evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories. The method employs a test structure that identical to the memory array whose gate oxide quality is to be determined. The cells of the test structure are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the defective cells while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells.
U.S. Pat. No. 6,066,952 (Nowak, et al.) demonstrates a method for measurement of a width of an undoped or lightly doped polysilicon line. The width measuring method includes generating a current in the polysilicon line with an energy source. The capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer is then measured. The line width of the polysilicon line is then determined from the measured capacitance.
U.S. Pat. No. 6,339,339 (Maeda) describes a method for evaluating the reliability of a thin film transistor (TFT), time coefficient, voltage coefficient and temperature coefficient are experimentally produced from negative bias thermal stress tests. The life of a TFT under negative bias thermal stress conditions is then evaluated.
U.S. Pat. No. 6,472,233 (Ahmed, et al.) teaches a MOS transistor test structure for capacitance-voltage measurements. The capacitance voltage measurements are employed for extracting polysilicon gate doping. The capacitance-voltage measurements analyze the test structure in strong inversion.
U.S. Pat. No. 6,011,404 (Ma, et al.) reveals a system and method for determining near-surface lifetimes and the tunneling field of a dielectric in a semiconductor.